mbuchman wrote:
The Rs and Cs seem kind of awkwardly placed… aren’t you supposed to put one right next to each ram chip and the uc? Or is that what C1 and C3 are for? (but nothing looks to be by “SAVE_SRAM”)You should get your artist on and hand route the next one. Autoroute looks funny, and makes tracing a real pain (which will make debugging crappy). But at least there is no shortage in vias for test points!
In a perfect world you want at least one decoupling cap next to critical components but on a small board with (relatively) short signal paths and a good LDO regulator with low output ripple it really shouldn’t be an issue. There is sufficient smoothing on the LDO which is at a different voltage than the VB, so fluctuations in VB voltage should not have much of an effect on the board. There are a couple caps that may seem random but I assure you it took me hours upon hours to find a place to put them among the mess of traces and vias. The caps were placed last. In the final design I am going to elongate the board which will give me more room for extra caps and such. I think people are forgetting that this is still a prototype and is by no means final.
I hand routed about 85% of that board. The initial pre-route was handled by an autorouter just to get me “in the ballpark” as far as which way to route certain bus signals. Then from there I had about 120 no-connects that I had to route, re-route, and re-route until I could fit everything in. I probably worked over 30 hours on the routing in total. I’m not really sure why it matters either way as long as it works…? I did spend an extra 3 or 4 hours trying to eliminate vias and with this many traces on a small 2-layer board it’s just not possible unless you’re a routing god or something.